Semiconductor memory device with divided source plate

Abstract

A semiconductor memory device includes a substrate including a cell region and a slimming region; a logic structure disposed over the substrate, the logic structure including logic circuit elements and bottom wiring lines electrically coupled to the logic circuit elements; a source plate disposed over the logic structure; a memory structure including a plurality of memory cells and a plurality of gate electrode layers, wherein the plurality of memory cells are disposed over the source plate of the cell region and a plurality of gate electrode layers are stacked over the source plate of the cell region and the slimming region to be separated from one another and are coupled to the plurality of memory cells; and a first slit cutting the source plate at a boundary between the cell region and the slimming region, wherein the source plate of the slimming region is floated regardless an operation of the memory cells and the logic circuit elements.