The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2021
Filed:
Dec. 17, 2019
Applicant:
Cerebras Systems Inc., Los Altos, CA (US);
Inventor:
Jean-Philippe Fricker, Los Altos, CA (US);
Assignee:
Cerebras Systems Inc., Los Altos, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 7/20 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); G03F 7/20 (2013.01); G03F 7/70466 (2013.01); G03F 7/70475 (2013.01); H01L 22/14 (2013.01); H01L 24/25 (2013.01); H01L 24/49 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54466 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/43985 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/49176 (2013.01); H01L 2224/49177 (2013.01); H01L 2224/94 (2013.01); H01L 2224/95001 (2013.01); H01L 2224/97 (2013.01);
Abstract
A system and method for fabricating distinct types of circuit connections on a semiconductor wafer includes fabricating, using a first photomask, a plurality of a first type of circuit connections for each of a plurality of distinct die of a semiconductor wafer; and fabricating, using a second photomask, a plurality of a second type of circuit connections between a plurality of distinct pairs of components of the semiconductor wafer, wherein each distinct pair of components includes at least one distinct die of the plurality of distinct die and one of a conductive pad and a sacrificial die.