The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Mar. 12, 2018
Applicant:

Drexel University, Philadelphia, PA (US);

Inventors:

Ioannis Savidis, Wallingford, PA (US);

Vaibhav Venugopal Rao, Philadelphia, PA (US);

Kyle Juretus, Quakertown, PA (US);

Assignee:

Drexel University, Philadelphia, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); G09C 1/00 (2006.01); H03L 7/089 (2006.01); H03B 5/12 (2006.01); H03L 7/091 (2006.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01); H03L 7/085 (2006.01); H03B 7/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/576 (2013.01); G09C 1/00 (2013.01); H03B 5/1212 (2013.01); H03B 5/1228 (2013.01); H03B 5/1246 (2013.01); H03L 7/0891 (2013.01); H03L 7/091 (2013.01); H04L 9/0866 (2013.01); H04L 9/3278 (2013.01); H03B 7/06 (2013.01); H03B 2200/0038 (2013.01); H03B 2201/0208 (2013.01); H03L 7/085 (2013.01); H04L 2209/08 (2013.01); H04L 2209/16 (2013.01);
Abstract

A key based technique that targets obfuscation of critical circuit parameters of an analog circuit block by masking physical characteristics of a transistor (width and length) and the circuit parameters reliant upon these physical characteristics (i.e. circuit biasing conditions, phase noise profile, bandwidth, gain, noise figure, operating frequency, etc.). The proposed key based obfuscation technique targets the physical dimensions of the transistors used to set the optimal biasing conditions. The widths and/or lengths of a transistor are obfuscated and, based on an applied key sequence, provides a range of potential biasing points. Only when the correct key sequence is applied and certain transistor(s) are active, are the correct biasing conditions at the target node set.


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