The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Nov. 14, 2016
Applicant:

Sharp Kabushiki Kaisha, Osaka, JP;

Inventors:

Takehisa Sakurai, Sakai, JP;

Kazuhiko Tsuda, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/133 (2006.01); G02F 1/1345 (2006.01); G09F 9/30 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3648 (2013.01); G02F 1/13306 (2013.01); G02F 1/13452 (2013.01); G02F 1/13454 (2013.01); G02F 2201/56 (2013.01); G09F 9/30 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0232 (2013.01); G09G 2310/0281 (2013.01);
Abstract

An array board includes a display area having a non-rectangular shape, TFTs disposed in the display area, a plurality of gate lines disposed in the display area and connected to the TFTs, a non-display area surrounding the display area, unit circuits disposed in the non-display area and connected to the gate lines, and a block connection line. The unit circuits are linearly arranged in the non-display area to form circuit blocks. The circuit blocks in the non-display area form a gate circuit portion in which at least two of the circuit blocks are away from each other in an oblique direction with respect to an arrangement direction of the unit circuits. The block connection line extends across the circuit blocks in the non-display area. The block connection line is connected to the circuit blocks.


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