The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Mar. 11, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Shohei Onishi, Kawasaki, JP;

Yoshiki Saito, Kawasaki, JP;

Yohei Hasegawa, Fuchu, JP;

Konosuke Watanabe, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/1009 (2016.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1009 (2013.01); G06F 12/0875 (2013.01); G06F 2212/45 (2013.01); G06F 2212/608 (2013.01);
Abstract

According to one embodiment, a memory system includes a cache configured to cache a part of a multi-level mapping table for logical-to-physical address translation, and a controller. The multi-level mapping table includes a plurality of hierarchical tables corresponding to a plurality of hierarchical levels. The table of each hierarchical level includes a plurality of address translation data portions. The controller sets a priority for each of the hierarchical level based on a degree of bias of reference for each of the hierarchical level, and preferentially caches each of the address translation data portions of a hierarchical level with a high priority into the cache, over each of the address translation data portions of a hierarchical level with low priority.


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