The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Apr. 27, 2016
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Qiong Cai, Palo Alto, CA (US);

Charles Johnson, Palo Alto, CA (US);

Paolo Faraboschi, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 11/30 (2006.01); G06F 12/1027 (2016.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 12/0811 (2016.01);
U.S. Cl.
CPC ...
G06F 9/5016 (2013.01); G06F 9/3851 (2013.01); G06F 9/46 (2013.01); G06F 9/4881 (2013.01); G06F 9/5027 (2013.01); G06F 9/52 (2013.01); G06F 11/30 (2013.01); G06F 12/0811 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/684 (2013.01);
Abstract

In one example, a central processing unit (CPU) with dynamic thread mapping includes a set of multiple cores each with a set of multiple threads. A set of registers for each of the multiple threads monitors for in-flight memory requests the number of loads from and stores to at least a first memory interface and a second memory interface by each respective thread. The second memory interface has a greater latency than the first memory interface. The CPU further has logic to map and migrate each thread to respective CPU cores where the number of cores accessing only one of the at least first and second memory interfaces is maximized.


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