The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Sep. 19, 2020
Applicant:
Nexchip Semiconductor Co., Ltd., Anhui, CN;
Inventor:
Geeng-Chuan Chern, Anhui, CN;
Assignee:
NEXCHIP SEMICONDUCTOR CO., LTD., Anhui, CN;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 27/11517 (2017.01); H01L 21/265 (2006.01); H01L 21/762 (2006.01); H01L 21/3213 (2006.01); H01L 21/02 (2006.01); H01L 21/283 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/788 (2013.01); H01L 21/02107 (2013.01); H01L 21/02697 (2013.01); H01L 21/265 (2013.01); H01L 21/283 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 27/11517 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 29/7831 (2013.01);
Abstract
The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.