The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Mar. 17, 2019
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Kazuyuki Ito, Yokohama, JP;

Koji Takaki, Higashihiroshima, JP;

Hidehiko Yabuhara, Kamakura, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/16 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4983 (2013.01); H01L 29/1608 (2013.01); H01L 29/7395 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes a semiconductor portion, a gate electrode, a source electrode, a first structure body, and a first insulating portion. The semiconductor portion includes SiC and includes first to third semiconductor regions. The first semiconductor region includes first to third partial regions. The second partial region is provided between the third partial region and the first partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The source electrode is electrically connected to the second semiconductor region. The first insulating portion includes a first insulating region and a second insulating region. The first insulating region is provided between the first partial region and the gate electrode. The second insulating region is provided between the second semiconductor region and the first structure body. The first structure body includes at least one of polysilicon or TiN.


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