The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Mar. 22, 2019
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventor:

Yoshiaki Toyoda, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0615 (2013.01); H01L 21/76224 (2013.01); H01L 27/088 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor integrated circuit includes: an n-type support layer; a p-type well region provided in an upper portion of the support layer; a p-type circuit side buried layer provided inside the well region; an n-type first and second terminal regions provided in an upper portion of the well region and above the circuit side buried layer; a p-type body region provided in an upper portion of the support layer; a control electrode structure provided in a gate trench; a p-type output side buried layer provided inside the body region so as to be in contact with the control electrode structure; and an n-type output terminal region provided in an upper portion of the body region and above the output side buried layer, wherein an output stage element having the output terminal region is controlled by a circuit element including the first and second terminal regions.


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