The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Feb. 18, 2020
Samsung Electronics Co., Ltd., Suwon-si, KR;
Miso Shin, Seoul, KR;
Myeongan Kwon, Hwaseong-si, KR;
Chungki Min, Hwaseong-si, KR;
Byoungho Kwon, Hwaseong-si, KR;
Boun Yoon, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.