The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Dec. 26, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung-Ho Do, Hwaseong-si, KR;

Woojin Rim, Hwaseong-si, KR;

Jisu Yu, Seoul, KR;

Jonghoon Jung, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 23/528 (2006.01); G03F 1/36 (2012.01); H01L 23/522 (2006.01); H01L 27/118 (2006.01); H01L 21/8238 (2006.01); H01L 23/485 (2006.01); H01L 27/092 (2006.01); G06F 30/398 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G03F 1/36 (2013.01); G06F 30/398 (2020.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/485 (2013.01); H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 27/11807 (2013.01); G06F 2119/18 (2020.01); H01L 23/5286 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01);
Abstract

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.


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