The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Aug. 07, 2017
Applicant:

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Hirotaka Oomori, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2006.01); H01L 29/78 (2006.01); H01L 23/373 (2006.01); H01L 23/492 (2006.01); H01L 23/538 (2006.01); H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/3736 (2013.01); H01L 23/492 (2013.01); H01L 23/5386 (2013.01); H01L 23/62 (2013.01); H01L 29/7827 (2013.01);
Abstract

A semiconductor module according to an embodiment includes a circuit substrate, a first vertical transistor having a first main electrode pad facing and coupled to a first input interconnect pattern of the circuit substrate, and having a first gate electrode pad coupled to a first control interconnect pattern of the circuit substrate, a second vertical transistor having a fourth main electrode pad facing and coupled to a second input interconnect pattern of the circuit substrate, and having a second gate electrode pad facing and coupled to a second control interconnect pattern of the circuit substrate, a surge voltage absorbing device connecting the first and second input interconnect patterns to absorb surge voltage, and a plate member connecting a second main electrode pad of the first vertical transistor and a third main electrode pad of the second vertical transistor.


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