The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Feb. 20, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Kensuke Yamamoto, Kanagawa, JP;

Kosuke Yanagidaira, Kanagawa, JP;

Fumiya Watanabe, Kanagawa, JP;

Shouichi Ozaki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 1/10 (2006.01); G11C 7/04 (2006.01); G11C 7/10 (2006.01); G11C 29/02 (2006.01); G11C 7/20 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 1/10 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01); G11C 7/04 (2013.01); G11C 7/1066 (2013.01); G11C 7/20 (2013.01); G11C 7/222 (2013.01); G11C 29/028 (2013.01); G11C 2029/4402 (2013.01); G11C 2207/2254 (2013.01);
Abstract

According to one embodiment, a nonvolatile memory includes a memory cell array including a first storage region and a second storage region, an input/output circuit configured to communicate with a memory controller, and a control circuit. The control circuit is configured to, upon receiving a first command from the memory controller, execute a first training operation related to the input/output circuit, and upon receiving a second command from the memory controller, store a first result of the first training operation in the first storage region.


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