The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Feb. 26, 2020
Realtek Semiconductor Corporation, Hsinchu, TW;
Shu-Yu Chang, Miaoli County, TW;
Shih-Jung Hsu, Hsinchu County, TW;
Han-Chieh Hsieh, Hsinchu, TW;
Yu-Cheng Lo, Taichung, TW;
Cheng-Yu Tsai, Hsinchu, TW;
REALTEK SEMICONDUCTOR CORPORATION, Hsinchu, TW;
Abstract
Disclosed is an IC layout design method capable of improving a result of an integrated circuit (IC) layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to an initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining an updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.