The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Sep. 11, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Akihiro Yamate, Tokyo, JP;

Yoshitaka Taki, Tokyo, JP;

Tatsuya Kamei, Tokyo, JP;

Yoichi Yuyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G11C 29/52 (2006.01); G11C 29/38 (2006.01); G06F 11/10 (2006.01); G06F 11/16 (2006.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0793 (2013.01); G06F 11/079 (2013.01); G06F 11/0724 (2013.01); G06F 11/0727 (2013.01); G06F 11/0751 (2013.01); G06F 11/0766 (2013.01); G06F 11/1068 (2013.01); G06F 11/1641 (2013.01); G06F 11/3055 (2013.01); G11C 29/38 (2013.01); G11C 29/52 (2013.01);
Abstract

Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.


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