The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Apr. 17, 2019
Applicants:

Dyna Image Corporation, New Taipei, TW;

Lite-on Semiconductor Corp., Taipei, TW;

Inventors:

Chun-Hsien Lin, New Taipei, TW;

Peng-Han Chan, New Taipei, TW;

Wen-Sheng Lin, New Taipei, TW;

Yu-Cheng Su, Taipei, TW;

Sheng-Cheng Lee, New Taipei, TW;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01J 1/44 (2006.01); G05B 19/042 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G05B 19/042 (2013.01); G01J 1/44 (2013.01); G06F 13/4282 (2013.01); G05B 2219/2231 (2013.01); G05B 2219/25257 (2013.01); G06F 2213/0016 (2013.01);
Abstract

A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (IC I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.


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