The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Apr. 20, 2018
Applicants:

Hefei Xinsheng Optoelectronics Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jianjun Wang, Beijing, CN;

Yuanyuan Liu, Beijing, CN;

Min Wang, Beijing, CN;

Rui Ma, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G09G 3/36 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136204 (2013.01); G09G 3/3677 (2013.01); G02F 2202/22 (2013.01); G09G 3/2096 (2013.01); G09G 3/3648 (2013.01); G09G 2300/0408 (2013.01); G09G 2310/0289 (2013.01); G09G 2310/08 (2013.01); G09G 2330/04 (2013.01); G09G 2330/08 (2013.01);
Abstract

The present disclosure discloses an electrostatic protection method, an electrostatic protection apparatus and a liquid crystal display. The electrostatic protection method includes: monitoring an interface signal of a timing control circuit and/or a level conversion circuit to determine whether the monitored signal is subjected to electrostatic interference; and when the electrostatic interference is detected, adjusting a timing control signal output by the timing control circuit to a gate driving circuit of an array substrate, wherein the level conversion circuit connects the timing control circuit to the gate driving circuit of the array substrate, and is configured to perform level conversion on an output signal output by the timing control circuit to the gate driving circuit of the array substrate.


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