The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2021
Filed:
Nov. 14, 2019
Xilinx, Inc., San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Apparatus and associated methods relate to a time-interleaved integrating sampling front-end circuit using integrating buffers. In an illustrative example, a circuit may include N sampling layers of circuits, an isampling layer of circuits of the N sampling layers of circuits may include: (a) Xbuffers configured to receive an analog signal, X≥1, and, (b) Ytrack-and-hold circuits, each track-and-hold circuit of the Ytrack-and-hold circuits is coupled to an output of a corresponding buffer of the X buffers, Y≥1, at least one buffer of the Xbuffers may include an integrating buffer, N≥i≥1. By implementing integrating buffers, a faster linear type of step settling response may be obtained as opposed to a slower exponential type of settling response.