The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Sep. 09, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Roman Staszewski, McKinney, TX (US);

Robert B. Staszewski, Dublin, IE;

Fuqiang Shi, San Jose, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H04W 56/00 (2009.01); G06F 17/10 (2006.01); H03L 7/197 (2006.01); H04B 1/04 (2006.01); G06F 9/30 (2018.01); G06F 7/60 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0992 (2013.01); G06F 7/605 (2013.01); G06F 9/30014 (2013.01); G06F 9/30032 (2013.01); G06F 9/30181 (2013.01); G06F 17/10 (2013.01); H03L 7/1974 (2013.01); H03L 7/1976 (2013.01); H04B 1/04 (2013.01); H04W 56/003 (2013.01); H03L 2207/50 (2013.01);
Abstract

A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.


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