The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

May. 23, 2019
Applicant:

Macom Technology Solutions Holdings, Inc., Lowell, MA (US);

Inventors:

Bengt Littmann, Newport Beach, CA (US);

George L. Barrier, IV, Lowell, MA (US);

Atul Gupta, Aliso Viejo, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/081 (2006.01); H04L 27/227 (2006.01); G04F 10/00 (2006.01); G06F 1/06 (2006.01); G06F 1/12 (2006.01); G06F 1/10 (2006.01); H04L 25/49 (2006.01); H04L 7/033 (2006.01); H04L 27/38 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0816 (2013.01); G04F 10/005 (2013.01); G06F 1/06 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); H04L 7/0058 (2013.01); H04L 7/0334 (2013.01); H04L 25/4917 (2013.01); H04L 27/2272 (2013.01); H04L 27/3809 (2013.01);
Abstract

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.


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