The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Nov. 11, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Woo Seo, Seoul, KR;

Youngsoo Shin, Daejeon, KR;

Jinwook Jung, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); H01L 27/02 (2006.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); G01R 31/31727 (2013.01); G01R 31/318541 (2013.01); H01L 27/0207 (2013.01); H03K 3/0372 (2013.01);
Abstract

A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.


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