The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

May. 03, 2019
Applicant:

Em Microelectronic-marin SA, Marin, CH;

Inventors:

Mathieu Coustans, Renens, CH;

Lubomir Plavec, Brno, CZ;

Mario Dellea, La Chaux-de-Fonds, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H02M 3/073 (2013.01); H02M 2003/075 (2013.01);
Abstract

The elementary pumping cell comprises an input (E) receiving an input voltage (Vin), a clock terminal (H) receiving a first clock signal (CK) and an output (S), a first capacitor (C) having a first terminal connected to the clock terminal and a second terminal, a first transistor (A) having a first source/drain terminal coupled to the input, a second source/drain terminal and a gate terminal, a second transistor (A) having a first source/drain terminal, a second source/drain terminal coupled to the input and a gate terminal coupled to the second terminal of the first capacitor, a third transistor (A) having a first source/drain terminal coupled to the first source/drain terminal of the second transistor, a second source/drain terminal coupled to the gate terminal of the second transistor and a gate terminal coupled to the input, and a fourth transistor (A) having a first source/drain terminal coupled to the second source/drain terminal of the first transistor, a second source/drain terminal coupled to the first source/drain terminal of the second and third transistors and a gate terminal coupled to the input. The gate terminal of the first transistor is coupled to the gate terminal of the second transistor.


Find Patent Forward Citations

Loading…