The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Oct. 23, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hui-Jung Kim, Seongnam-si, KR;

Keun Nam Kim, Yongin-si, KR;

Yoo Sang Hwang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10852 (2013.01); H01L 21/31144 (2013.01); H01L 23/5223 (2013.01); H01L 27/10814 (2013.01); H01L 28/90 (2013.01); H01L 28/91 (2013.01);
Abstract

A method for fabricating a semiconductor device includes stacking a first mold layer and a first supporter layer, forming a first supporter pattern by etching the first supporter layer to expose the first mold layer, forming an insulating layer to cover the exposed first mold layer and the first supporter pattern, stacking a second mold layer and a second supporter layer on the insulating layer, forming a contact hole by dry-etching the second supporter layer, the second mold layer, the insulating layer, the first supporter pattern, and the first mold layer, forming a lower electrode within the contact hole, removing the first mold layer, the second mold layer, and the insulating layer, and forming an upper electrode on the lower electrode and the first supporter pattern, wherein, during the dry-etching, dry etching rates of the first supporter pattern and the insulating layer are the same.


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