The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Jul. 24, 2019
Applicant:

Fuji Electric Co., Ltd., Kawasaki, JP;

Inventors:

Takeyoshi Nishimura, Matsumoto, JP;

Isamu Sugai, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01);
Abstract

Provided are a semiconductor element and a semiconductor device capable of reducing possibilities of malfunctions and breakdowns due to temperature rise. A semiconductor element () includes a first MOS transistor (Tr), a second MOS transistor (Tr), and a temperature detecting element (TD) that are provided on a semiconductor substrate (SB). The first MOS transistor (Tr) includes an n-type source region (), an n-type first semiconductor region () arranged away from the source region () and a p-type well region () arranged between the source region () and the first semiconductor region (). The second MOS transistor (Tr) includes an n-type source region () an n-type second semiconductor region () arranged away from the source region (), and a p-type well region () arranged between the source region () and the second semiconductor region (). The first semiconductor region () is connected to the second semiconductor region ().


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