The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Nov. 25, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Sang Eun Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 22/12 (2013.01); H01L 23/49838 (2013.01); H01L 23/528 (2013.01); H01L 25/50 (2013.01); H01L 22/14 (2013.01); H01L 23/562 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01);
Abstract

A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance.


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