The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2021
Filed:
Apr. 09, 2018
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Rwik Sengupta, Austin, TX (US);
Mark Rodder, Dallas, TX (US);
Joon Goo Hong, Austin, TX (US);
Titash Rakshit, Austin, TX (US);
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/535 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/78 (2013.01);
Abstract
An integrated circuit including a series of field effect transistors. Each field effect transistor includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate on the channel region, a gate contact on the gate at an active region of the gate, a source contact on the source region, and a drain contact on the drain region. Upper surfaces of the source and drain contacts are spaced below an upper surface of the gate by a depth.