Shared source line memory architecture for flash cell byte-alterable high endurance data memory

Abstract

A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.