The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Mar. 30, 2020
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Takehiro Yoshida, Kyoto, JP;

Shun Fukushima, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/00 (2006.01); H02M 3/335 (2006.01); G05F 1/00 (2006.01); G11C 7/22 (2006.01); G11C 16/30 (2006.01); G06F 1/04 (2006.01); H03L 7/081 (2006.01); H03L 7/14 (2006.01); G11C 16/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G06F 1/04 (2013.01); G11C 16/12 (2013.01); G11C 16/30 (2013.01); H03L 7/0814 (2013.01); H03L 7/14 (2013.01);
Abstract

A clock generation circuit, which generates an output clock using an external clock as a target clock, includes a circuit arranged to change the output clock to high level in synchronization with an up edge of the target clock, circuits arranged to generate first and second ramp voltages with a period of interval between neighboring up edges of the target clock, and a circuit arranged to hold a comparison voltage corresponding to a second ramp voltage when an up edge of the target clock occurs. The level of the output clock is changed from high level to low level based on a comparison result between the first ramp voltage and the comparison voltage.


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