The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

May. 07, 2018
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Naobumi Toyomura, Kanagawa, JP;

Yusuke Onoyama, Kanagawa, JP;

Junichi Yamashita, Tokyo, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); G09G 3/3291 (2016.01); G09G 3/3266 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/3266 (2013.01); G09G 3/3291 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2300/0876 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/043 (2013.01);
Abstract

Provided is a display device in which a pixel circuit is arranged, the pixel circuit including a P channel type driving transistor that drives a light emitting unit, a sampling transistor that samples a signal voltage, a light emission control transistor that controls light emission/non-light emission of the light emitting unit, a holding capacitor that is connected between a gate electrode and a source electrode of the driving transistor, and holds the signal voltage written by the sampling by the sampling transistor, and an auxiliary capacitor that is connected between the source electrode of the driving transistor and a node having fixed potential, the display device including: a current path that flows a current flowing in the driving transistor in a non-light emission period of the light emitting unit into a predetermined node.


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