The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Jun. 01, 2017
Applicant:

Seagate Technology Llc, Cupertino, CA (US);

Inventor:

Timothy Canepa, Los Gatos, CA (US);

Assignee:

Seagate Technology LLC, Fremont, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/40 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4004 (2013.01); G06F 13/4068 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01);
Abstract

Method and apparatus for managing a non-volatile memory (NVM). In some embodiments, a memory module has a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A controller is adapted to communicate commands and data to the MME circuit via an intervening data bus. The controller operates to reset the MME circuit by issuing a reset command to the MME circuit over the data bus, activating a decoupling circuit coupled between the data bus and a reference line at a reference voltage level to remove capacitance from the data bus resulting from the reset command, and subsequently sensing a voltage on the data bus. In some cases, multiple MME circuits and NVMs may be arranged on a plurality of flash dies which are concurrently reset by the controller.


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