The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2021
Filed:
Aug. 29, 2018
Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;
Yves Durand, Saint-Ismier, FR;
Christian Bernard, Saint Etienne de Crossey, FR;
Abstract
A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g., restart mode and pause mode) of the at least one microprogram stored in the register may be configurable. Exemplary microprograms can (1) provide image processing parameters including sizes of columns of image blocks, (2) provide image processing parameters including numbers of successive pieces of data to be processed which are to be written to successive addresses in the shared local memory, and (3) utilize a sequential write mode and/or an absolute-offset write mode. Microprograms may be selected based on an identifier included in a header of each packet.