The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Sep. 24, 2018
Applicant:

Salesforce.com, Inc., San Francisco, CA (US);

Inventors:

Luc Marcel Giavelli, San Francisco, CA (US);

Joshua James Luft-Glidden, San Francisco, CA (US);

Radhika Nair, San Francisco, CA (US);

Fabrice Talbot, San Francisco, CA (US);

Srinivasa Gopaladasu, San Francisco, CA (US);

Venkata Kolla, San Francisco, CA (US);

Lucas Pfister, Millbrae, CA (US);

Chintan Tank, Dublin, CA (US);

Chaitanya Bhatt, San Francisco, CA (US);

Assignee:

salesforce.com, inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0622 (2013.01); G06F 3/067 (2013.01); G06F 3/0637 (2013.01); G06F 3/0644 (2013.01); G06F 3/0659 (2013.01);
Abstract

A processor can determine that a set of the memory cells is controlled by signals from a first portal. The processor can determine a function of a second portal in a relationship between the first portal and the second portal. The processor can cause, in response to a determination that the function of the second portal is a specific function, a memory control circuitry to be configured so that a subset, of the set, is controlled also by signals from the second portal. The processor can determine a function of a third portal in a relationship between the first portal and the third portal. The processor can cause, in response to a determination that the function of the third portal is the specific function, the memory control circuitry to be configured so that the subset, of the set, is controlled also by signals from the third portal.


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