Skew correction for source synchronous systems

Abstract

A circuit may perform a skew correction process that positions clock pulses of an output clock signal in respective target sampling positions. The circuit may receive an input clock signal and an input data signal and select one of a plurality of predetermined skew cases for the input clock signal and the input data signal. In addition, the circuit may performing timing relationship measurements for transition permutations of the clock signal and the data signal. The circuit may determine which of the input clock signal and the input data signal to delay and an amount of the delay based on the selected skew case and the timing relationship measurements. An output of the circuit may delay the input clock signal or the input data signal according to the determinations, which centers the sampling transitions of the clock signal in target sampling positions.