The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Oct. 19, 2017
Applicants:

Exact Biochip Corporation, New Taipei, TW;

National Chiao Tung University, Hsinchu, TW;

Inventors:

Jeng-Tzong Sheu, Hsinchu, TW;

Chih-Wei Chen, Hsinchu, TW;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/00 (2006.01); G01N 33/543 (2006.01); H01L 29/06 (2006.01); H01L 29/739 (2006.01); H01L 29/423 (2006.01); G01N 27/414 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
G01N 33/54373 (2013.01); G01N 27/4145 (2013.01); G01N 27/4146 (2013.01); G01N 27/4148 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66356 (2013.01); H01L 29/66439 (2013.01); H01L 29/66772 (2013.01); H01L 29/7391 (2013.01); H01L 29/775 (2013.01); H01L 29/458 (2013.01);
Abstract

Provided is a biological sensing system, including a nanowire field-effect transistor and a sensing chip. A gate terminal of the nanowire FET surrounds a gate of a silicon nanowire or a gate of a silicon nanobelt, diameter of the silicon nanowire is less than 20 nm. A sensing electrode of the sensing chip is coupled to the gate terminal of the nanowire FET. An area ratio of an electrode area of the sensing electrode to a total sensing chip area, a thickness ratio of an oxide thickness of sensing electrode to a bulk oxide dielectric film thickness of the sensing chip and a capacitance ratio of an electrode capacitor of the sensing electrode to a gate capacitor of the silicon nanowire or a gate capacitor of the silicon nanobelt are optimized by means of an equivalent circuit so that potential coupling efficiency between sensing electrode and gate is optimized.


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