The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jul. 18, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Hyeok-Jong Lee, Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/357 (2011.01); H04N 5/378 (2011.01); H03M 1/08 (2006.01); H03M 1/14 (2006.01); H03M 1/12 (2006.01); H04N 5/363 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3575 (2013.01); H03M 1/0872 (2013.01); H03M 1/1245 (2013.01); H03M 1/144 (2013.01); H04N 5/363 (2013.01); H04N 5/378 (2013.01);
Abstract

A digital correlated double sampling (CDS) circuit includes a first latch circuit, a first converting circuit, a second converting circuit, a second latch circuit, and a calculating circuit. The first latch circuit latches an input phase shift code based on a first control signal to store first and second phase shift codes. The first converting circuit converts the first and second phase shift codes into first and second Gray codes. The second converting circuit converts the first Gray code and the second Gray code into a first binary code and a second binary code. The second latch circuit latches an output of the second converting circuit based on a second control signal to store the first binary code. The calculating circuit operates on the first binary code and the second binary code to generate a third binary code, and outputs the third binary code.


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