The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jan. 03, 2019
Applicant:

Short Circuit Technologies Llc, Rochester, NY (US);

Inventors:
Assignee:

Short Circuit Technologies LLC, Rochester, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 1/38 (2006.01); H03F 1/26 (2006.01); H03F 1/56 (2006.01); H03F 3/19 (2006.01); H04B 1/7097 (2011.01);
U.S. Cl.
CPC ...
H03F 1/26 (2013.01); H03F 1/56 (2013.01); H03F 3/19 (2013.01); H04B 1/7097 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/372 (2013.01); H03F 2200/451 (2013.01); H04B 2201/709709 (2013.01);
Abstract

A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.


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