The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2021
Filed:
Jun. 04, 2020
Applicant:
Socionext Inc., Yokohama, JP;
Inventor:
Hiroyuki Shimbo, Yokohama, JP;
Assignee:
SOCIONEXT INC., Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01); B82Y 10/00 (2011.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 29/775 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); B82Y 10/00 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 27/11807 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 21/823807 (2013.01); H01L 21/823871 (2013.01); H01L 29/775 (2013.01);
Abstract
In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.