The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Nov. 01, 2018
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Shinya Takashima, Hachioji, JP;

Katsunori Ueno, Matsumoto, JP;

Masaharu Edo, Tokorozawa, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/04 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 21/223 (2006.01); H01L 21/324 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/02389 (2013.01); H01L 21/2233 (2013.01); H01L 21/3245 (2013.01); H01L 29/045 (2013.01); H01L 29/0865 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/66712 (2013.01); H01L 29/7802 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01);
Abstract

A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.


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