The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jul. 21, 2019
Applicant:

Meridian Innovation Pte Ltd, Singapore, SG;

Inventors:

Piotr Kropelnicki, Singapore, SG;

Ilker Ender Ocak, Singapore, SG;

Paul Simon Pontin, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); G01J 5/04 (2006.01); G01J 5/12 (2006.01); G01J 5/02 (2006.01); B81C 1/00 (2006.01); G01J 5/08 (2006.01); G01J 5/16 (2006.01); H01L 31/0224 (2006.01); H01L 31/09 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14669 (2013.01); B81C 1/00 (2013.01); G01J 5/024 (2013.01); G01J 5/0225 (2013.01); G01J 5/046 (2013.01); G01J 5/048 (2013.01); G01J 5/0853 (2013.01); G01J 5/12 (2013.01); G01J 5/16 (2013.01); H01L 27/146 (2013.01); H01L 27/14612 (2013.01); H01L 27/14629 (2013.01); H01L 27/14643 (2013.01); H01L 27/14649 (2013.01); H01L 31/0224 (2013.01); H01L 31/09 (2013.01); G01J 2005/123 (2013.01);
Abstract

Device and method of forming the device are disclosed. The method includes providing a substrate prepared with a complementary metal oxide semiconductor (CMOS) region and a sensor region. A substrate cavity is formed in the substrate in the sensor region, the substrate cavity including cavity sidewalls and cavity bottom surface and a membrane which serves as a substrate cavity top surface. The cavity bottom surface includes a reflector. The method also includes forming CMOS devices in the CMOS region, forming a micro-electrical mechanical system (MEMS) component on the membrane, and forming a back-end-of-line (BEOL) dielectric disposed on the substrate having a plurality of interlayer dielectric (ILD) layers. The BEOL dielectric includes an opening to expose the MEMS component. The opening forms a BEOL cavity above the MEMS component.


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