The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Mar. 29, 2018
Applicants:

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Wei Zhang, Beijing, CN;

Hui Li, Beijing, CN;

Tianlei Shi, Beijing, CN;

Jonguk Kwak, Beijing, CN;

Yezhou Fang, Beijing, CN;

Wenlong Zhang, Beijing, CN;

Xu Zhang, Beijing, CN;

Zhijun Niu, Beijing, CN;

Ruize Jiang, Beijing, CN;

Yanwei Ren, Beijing, CN;

Yu Liu, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/12 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01); G02F 1/1362 (2006.01); H01L 27/32 (2006.01); G02F 1/1368 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G02F 1/136204 (2013.01); H01L 27/0288 (2013.01); H01L 27/1244 (2013.01); H01L 27/1259 (2013.01); H01L 27/3265 (2013.01); G02F 1/1368 (2013.01); H01L 27/3276 (2013.01);
Abstract

An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.


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