The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Aug. 27, 2018
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Hiroki Sasaki, Aichi-ken, JP;

Atsushi Murakoshi, Mie-ken, JP;

Ryuji Ohba, Mie-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 23/532 (2006.01); G11C 7/06 (2006.01); H01L 21/768 (2006.01); G11C 8/14 (2006.01); H01L 29/792 (2006.01); G11C 8/10 (2006.01); G11C 7/18 (2006.01); H01L 29/788 (2006.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 7/06 (2013.01); G11C 7/18 (2013.01); G11C 8/10 (2013.01); G11C 8/14 (2013.01); H01L 21/76897 (2013.01); H01L 23/5329 (2013.01); H01L 27/1157 (2013.01); H01L 29/7926 (2013.01); H01L 27/11556 (2013.01); H01L 29/7889 (2013.01);
Abstract

A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.


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