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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10903120 B1

PDFFull Text
Date of Patent:
Jan. 26, 2021

Filed:

Sep. 28, 2018

Semiconductor wafer dicing crack prevention using chip peripheral trenches

Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Arno Zechmann, Villach, AT;

Gianmauro Pozzovivo, Sattendorf, AT;

Assignee:

Infineon Technologies Austria AG, Villach, AT;

Attorney:

Murphy, Bilak & Homiller, PLLC

Primary Examiner:

Long Pham

Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 29/04 (2006.01); H01L 23/00 (2006.01); H01L 29/778 (2006.01); H01L 29/06 (2006.01); H01L 23/544 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/6609 (2013.01); H01L 29/66462 (2013.01); H01L 29/7783 (2013.01); H01L 2223/54453 (2013.01);
Abstract

A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.

Find Patent Forward Citations

Zechmann, Arno. (2021). Semiconductor wafer dicing crack prevention using chip peripheral trenches (U.S. Patent No. 10903120). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10903120

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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