The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Nov. 29, 2018
Applicant:

Sumco Corporation, Tokyo, JP;

Inventors:

Ikuhiro Nakamura, Tokyo, JP;

Keiichi Takanashi, Tokyo, JP;

Assignee:

SUMCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/66 (2006.01); H01L 21/68 (2006.01); H01L 21/677 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67259 (2013.01); H01L 21/67718 (2013.01); H01L 21/68 (2013.01); H01L 21/68735 (2013.01); H01L 22/34 (2013.01);
Abstract

Provided is a semiconductor wafer placement position determination method making it possible to measure a position deviation at a placement position of a semiconductor wafer when using a susceptor that is N-fold symmetric with respect to the center of the susceptor as a rotation axis. In this method, an opening edge of a counterbore portion of the susceptor is N-fold symmetric with respect to the center of the susceptor as a rotation axis (N≥2). This method includes: a measurement step of measuring, while rotating the susceptor on which the semiconductor wafer is placed, a gap distance between a periphery of the semiconductor wafer and the opening edge; a first calculation step of performing, based on variation of the gap distance, period regression analysis; and a second calculation step of determining the position deviation based on an amplitude of a trigonometric function obtained by the first calculation step.


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