The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Nov. 08, 2017
Applicant:

Massachusetts Institute of Technology, Cambridge, MA (US);

Inventors:

Jeehwan Kim, Cambridge, MA (US);

Kyusang Lee, Cambridge, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 21/02 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02444 (2013.01); H01L 21/02389 (2013.01); H01L 21/02455 (2013.01); H01L 21/02458 (2013.01); H01L 21/02485 (2013.01); H01L 21/02502 (2013.01); H01L 21/683 (2013.01); H01L 21/762 (2013.01); H01L 21/02392 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a first epitaxial layer on a first substrate. The first substrate includes a first semiconductor material having a first lattice constant and the first epitaxial layer includes a second semiconductor material having a second lattice constant different from the first lattice constant. The method also includes disposing a graphene layer on the first epitaxial layer and forming a second epitaxial layer comprising the second semiconductor material on the graphene layer. This method can increase the substrate reusability, increase the release rate of functional layers, and realize precise control of release thickness.


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