The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jul. 12, 2019
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Se Chang Park, Chungcheongbuk-do, KR;

Jong Wook Kim, Chungcheongbuk-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/065 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); G11C 16/349 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01);
Abstract

A memory system includes a memory cell array including a plurality of memory cells; a peripheral circuit configured to apply a read voltage to a selected word line coupled to a selected memory cell among the memory cells, and apply a pass voltage to unselected word lines coupled to unselected memory cells other than the selected memory cell among the memory cells, during a read operation; and a controller configured to control the peripheral circuit, and apply a variable voltage level of the pass voltage based on status information of a target memory block which is the target of the read operation.


Find Patent Forward Citations

Park, Se. (2021). Memory system varying pass voltage based on erase count of target memory block and operating method thereof (U.S. Patent No. 10902924). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10902924

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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