The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

May. 15, 2020
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Noboru Shibata, Kawasaki, JP;

Kazuaki Isobe, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H01L 27/11556 (2017.01); G11C 16/26 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); G11C 16/14 (2006.01); H01L 27/11524 (2017.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); H01L 21/768 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 21/311 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 7/1006 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 11/5642 (2013.01); G11C 16/0408 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 21/28568 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76879 (2013.01); H01L 29/7883 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n−1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n−1) layers of select gate layers include first to (2×(n−1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n−1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k−2)th select gates. The nth string unit is selected by the nth to (2×(n−1))th select gates.


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