The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Jun. 15, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Steven Craig Bartling, Plano, TX (US);

Sudhanshu Khanna, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/14 (2006.01); G06F 1/32 (2006.01); G06F 11/10 (2006.01); G11C 14/00 (2006.01); G06F 12/02 (2006.01); G06F 9/4401 (2018.01); G11C 7/22 (2006.01); G06F 1/3203 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); H03K 3/3562 (2006.01); G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 1/3203 (2013.01); G06F 1/3234 (2013.01); G06F 1/3275 (2013.01); G06F 1/3287 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 9/4401 (2013.01); G06F 9/4406 (2013.01); G06F 11/1032 (2013.01); G06F 11/1438 (2013.01); G06F 11/1469 (2013.01); G06F 12/0238 (2013.01); G06F 13/00 (2013.01); G11C 14/00 (2013.01); H03K 3/3562 (2013.01); Y02D 10/00 (2018.01); Y02D 30/50 (2020.08);
Abstract

A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to storea machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.


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