The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10902173 B1

Date of Patent:

Jan. 26, 2021

Filed:

Jun. 12, 2019

System for designing integrated circuit using extracted model parameter and method of manufacturing integrated circuit using the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Yo-han Kim, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Mohammed Alam

Int. Cl.

CPC ...

G06F 30/392 (2020.01); G06F 30/20 (2020.01); G06F 30/30 (2020.01); G06F 119/18 (2020.01);

U.S. Cl.

CPC ...

G06F 30/392 (2020.01); G06F 30/20 (2020.01); G06F 30/30 (2020.01); G06F 2119/18 (2020.01);

Abstract

A method of manufacturing an integrated circuit in which a semiconductor device is provided includes simulating electrical characteristics of the semiconductor device according to a received process variable, by using a model parameter file including a plurality of model parameters, generating semiconductor device layout data based on a result of the simulation, and manufacturing the integrated circuit according to a semiconductor device layout based on the semiconductor device layout data, wherein the plurality of model parameters are stored in the model parameter file in a form of at least one function regarding the process variable.

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