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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10902168 B1

PDFFull Text
Date of Patent:
Jan. 26, 2021

Filed:

Jan. 04, 2018

Computer-implemented method and computing system for designing integrated circuit by considering timing delay

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong-pil Lee, Suwon-si, KR;

Bong-il Park, Seongnam-si, KR;

Moon-su Kim, Gimpo-si, KR;

Sun-ik Heo, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Suresh Memula

Int. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/3312 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

A computer-implemented method and a computing system for designing an integrated circuit are provided. The method includes generating wire data corresponding to a net included in an integrated circuit, the wire data including metal layer information of a wire corresponding to the net and physical information of the wire, performing timing analysis using the physical information of the wire included in the wire data to generate timing analysis data, and changing a layout of the integrated circuit according to the timing analysis data.

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