The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Jan. 28, 2020
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Carlos Joao Marques Martins, Munich, DE;

Markus Bader, Merching, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/00 (2006.01); H03K 17/082 (2006.01); G05B 19/04 (2006.01); H02M 1/08 (2006.01); H02M 7/5387 (2007.01); H02P 27/08 (2006.01); H03K 17/18 (2006.01); H03K 17/28 (2006.01); H03K 17/56 (2006.01); H03K 17/94 (2006.01); H03K 17/693 (2006.01); H03K 17/08 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01); G05B 19/04 (2013.01); H02M 1/08 (2013.01); H02M 7/5387 (2013.01); H02P 27/08 (2013.01); H03K 17/18 (2013.01); H03K 17/28 (2013.01); H03K 17/56 (2013.01); H03K 17/693 (2013.01); H03K 17/94 (2013.01); H03K 2017/0806 (2013.01); H03K 2217/0027 (2013.01);
Abstract

A description is given below of an intelligent semiconductor switch and also a method for operating an intelligent semiconductor switch integrated in a chip package. In accordance with one exemplary embodiment, the method comprises, in a first mode, in which a state control signal having a first logic level is received at a control terminal of the chip package, driving a first and a second semiconductor switch of a half-bridge in accordance with an input signal received at an input terminal of the chip package. In a second mode, in which a state control signal having a second logic level is received at the control terminal of the chip package, the method comprises setting an operating parameter depending on a pulse pastern of the input signal received at the input terminal.


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